EuTOPIA: Facilitating Processor-Based DPR Systems for non-DPR Experts

Dynamic Partial Reconfiguration (DPR) allows the targeted FieldProgrammable Array (FPGA) to selectively update portions of the programmable logic while the remainder of the fabric stays active. Previously, designers were required to manually create DPR systems with minimal support from Computer Aided Design (CAD) tools. Xilinx ® ’s PlanAhead TM software now automates much of the DPR system generation process for ISE-based DPR systems. This paper presents EuTOPIA (EDK TO PlanAhead Implementation Automation), a CAD tool that extends the automation in Xilinx’s current DPR design flow to include microprocessor based designs. Given an architecture described in Xilinx’s Embedded Design Kit (EDK), EuTOPIA automates the process of converting it into a PlanAhead project for a DPR design. EuTOPIA abstracts the low level details of DPR implementation so that designers need only have nominal knowledge of the underlying process to create their initial DPR system. EuTOPIA is shown to reduce implementation time by a factor of 18 times over manual implementations by experienced designers, and can be further increased for novice designers. Over the design-cycle of a product where designers may generate tens or even hundreds of different implementations of their DPR design, these time savings could be extremely significant.